1. Technical Field
The present invention relates to memory devices, and more specifically, to a method and circuit for writing sampled input data to memory cells in a semiconductor memory device having a double data rate (DDR) scheme.
2. Discussion of the Related Art
As the demand for higher speed semiconductor devices increases, a double data rate data sampling scheme (hereinafter, referred to as “DDR”) that is capable of inputting (writing) or outputting (reading) data at a rising edge as well as a falling edge of an external clock signal, is being increasingly employed. Data is sampled to allow two data to be read or written during one external clock cycle. Thus, Double Data Rate (DDR) is achieved by using both the rising and falling edges of the clock to transfer data.
In the case of a DDR semiconductor memory device, for example, a DDR static random access memory (DDR SRAM) device, data is inputted/outputted in a burst mode in synchronization with each of rising and falling edges of the external clock signal. In a write operation of the SRAM device, data inputted (written) in response to a write command signal, for example, input data is stored in a temporary register in response to a second write command signal, and the stored data is written to memory cells of the device in response to a third write command signal. Generally, the DDR SRAM device uses a clock centered (CC) mode in which, when data is written to the device, four data are successively inputted (written) to the device in synchronization with an external clock signal in a next cycle after a write command signal is inputted to the device, data is inputted at a center of the external clock signal in synchronization with the rising edge or falling edge of the external clock signal, and a sampling clock signal is generated at the rising edge or the falling edge of the external clock signal. Also, in a clock aligned (CA) mode, data is inputted to the device at the rising or falling edge of the external clock signal in synchronization with the rising edge or the falling edge of the external clock signal and a sampling clock signal is generated at the center of the external clock signal.
A conventional method and device for sampling data in a semiconductor memory device are disclosed in U.S. Pat. No. 6,538,483 entitled “Method and apparatus for data sampling,” and a circuit for controlling setup and hold margins in a semiconductor memory device is disclosed in U.S. Pat. No. 6,232,811 entitled “Circuit for controlling setup/hold time of semiconductor device.”
FIG. 1 is a diagram partially showing a circuit of the prior art for explaining a method for sampling data in a DDR SRAM device. FIG. 2 is a timing diagram showing a data sampling operation in a CC mode of the DDR SRAM device of FIG. 1. FIG. 3 is a timing diagram showing a data sampling operation in a CA mode of the DDR SRAM device of FIG. 1.
Hereinafter, a prior art method for sampling and writing data in a DDR SRAM device using a a single path control signal will be described in brief with reference to the accompanying drawings.
Referring to FIG. 1, a prior art path control signal generating circuit 100, used for data sampling, is composed generally of a basic CMOS flip flop comprised essentially of inverters (e.g., in inverting latches 110, 120) and of transmission (pass) gates (102, 104) having an input A0 to be sampled and latched and a having single output (path control signal) PS. A first (inverting) latch 112 latches (and inverts) an address signal A0 input via the transmission (pass) gate 102 controlled by the sampling clock signal CLK and its complement; the first pass gate 102 passes the address signal A0 when during the active level of the sampling clock signal CLK; the first latch 110 stores the address signal A0 output from (passed by) the first pass gate in a latched form and inverts the address signal A0; second and third inverters 114 and 116 continuously buffer the inverted address signal A0 (output from the first latch 110); a second pass gate 104 passes the buffered inverted address signal A0 (output from the third inverter 116) when receiving the active level of the sampling clock signal CLK; a second latch 120 stores the inverted address signal A0 (received via the second pass gate 104) in a latched form and inverts it to output a latched address signal A0 to the fourth inverter 118; the fourth inverter 118 inverts the latched address signal A0 and outputs the path control signal PS. The path control signal generating circuit 100 generates the path control signal PS the value of which depends on logical states of the sampling clock signal CLK and the address signal A0, both of which are generated in synchronization with an external clock signal (see FIGS. 2, 3).
Referring to FIG. 2, in the CC mode of a DDR SRAM device including the conventional path control signal generating circuit 100 of FIG. 1, four of first to fourth data D1_H, D1_L, D2_H and D2_L are successively inputted to the device in synchronization with a rising edge or a falling edge of the external clock signal (ECLK) in response to a write commands. A first sampling clock signal SCLK1 is generated in synchronization with each rising edge (transition) of the external clock signal (ECLK), to enable the first data D1_H to be sampled (and latched) and a path control signal PS having a “0” state is generated in synchronization with an active level of the first sampling clock signal SCLK1, causing the first (sampled) data D1_H to be linked to a first path Path1. Next, a second sampling clock signal SCLK2 is generated (in synchronization with each falling edge (transition) of the external clock signal ECLK), enabling the second data D1_L to be sampled (and latched),) to cause the second data D1_L to be linked to a second path Path2, while the path control signal (PS) having a “0” state is generated (in synchronization with the first sampling clock signal SCLK1). A writing clock signal WCLK is generated in synchronization with selected (e.g., third and fourth) rising edges of the external clock signal, so that the first data D1_H on the first path and the second data D1_L on the second path are written to the memory cells. Subsequently, the first sampling clock signal SCLK1 is generated (in synchronization with a second rising edge of the external clock signal ECLK), enabling the third data D2_H to be sampled, and the path control signal having a “1” state is generated (in synchronization with the first sampling clock signal SCLK1) so that the third data D2_H is linked to the second path Path2, and to cause the second data D1_L to be linked to the first path Path1.
The data to be written to the memory cells is changed from the first data D1_H to the second data D1_L on the first path1 and from the second data D1_L to the third data D2_H on the second path2 at a time point where the write clock signal WCLK is generated, resulting in an insufficient hold margin which may cause an error upon writing data. Conventionally, in order to solve this problem, the data on the first and second paths are delayed (relative to the writing clock WCLK) by a predetermined time and then written.
Referring to FIG. 3, in the CA mode of the DDR SRAM device including the conventional path control signal generating circuit 100 of FIG. 1, four of first to fourth data D1_H, D1_L, D2_H and D2_L are successively inputted to the device in synchronization with the rising edge or the falling edge of the external clock signal and a write command. Subsequently, a first sampling clock signal SCLK1 is generated (at a first center of a Hi external clock signal in synchronization with a first rising edge of the external clock signal), enabling the first data D1_H to be sampled, and a path control signal having a “0” state is generated (in synchronization with the first sampling clock signal SCLK1), so that the first data D1_H is sampled to the first path Path1. Next, a second sampling clock signal SCLK1 is generated (at a center of a Low external clock signal in synchronization with a first falling edge of the external clock signal), enabling the second data D1_L to be sampled, and the path control signal having a “0” state is generated (in synchronization with the first sampling clock signal SCLK1) to cause the second data D1_L to be linked to the second path Path2. A write clock signal WCLK is generated (in synchronization with the second and third rising edges of the external clock signal), so that the first data D1_H on the first path and the second data D1_L on the second path are written to the memory cell.
Subsequently, the first sampling clock signal SCLK1 is again generated (at a center of a Hi external clock signal ECLK in synchronization with a second rising edge of the external clock signal ECLK), enabling the third data D2_H to be sampled, and the path control signal having a “1” state is generated (in synchronization with the first sampling clock signal SCLK1), so that the third data D2_H is linked to the second path Path2 and the second data D1_L is linked to the first path Path1.
As a result, there is a problem that a sufficient setup margin M1 cannot be secured because the second data D1_L on the second path Path2 is positioned at a point of ¼ or less of the external clock cycle period when the write clock signal WCLK I is generated. Thus, there can arise a problem that an error is caused upon writing data because a setup margin in a CA mode is insufficient. The problem is great where the SRAM device has a high operation frequency and data on the first and second paths are delayed and then used to secure the hold margin in the above-stated CC mode.